Design Verification Engineer

DESIGN VERIFICATION ENGINEERBENGALURU, INDIA : HYBRIDAbout the role:We are seeking a seasoned Design Verification Engineer with a strong backgroundin building testbenches and writing test sequences for complex IPs. The idealcandidate will play a key role in shaping our technology portfolio, bringing expertiseand creativity to our solutionsResponsibilities​: Create test plans for highly configurable IPs meant to provide interconnectivitybetween components across an SoC, chiplet, or multi-chiplet systems Write UVM/SystemVerilog code to implement the test plan, checkers, andscoreboards Collaborate with software teams to define and implement configurable testbenches Work with design teams test plans, failure debug, coverage, etc.​Qualifications and Preferred Skills​ BS, MS in Electrical Engineering,Computer Engineering or Computer Science 8+ years and current hands-on experience in block-level/IP-level/SoC-levelverification Proficiency in Verilog, SystemVerilog Familiarity with industry-standard EDA tools for simulation and debug Deep experience with UVM-based test benches Experience with modern programming languages like Python Knowledge of Arm AMBA protocols such as AXI, APB, and AHB Understanding of Arm CHI protocol is a plus Experience on working with IPs for caches, cache coherency, memorysubsystems, interconnects and NoCs Experience with formal verification techniques, emulation platforms is a plus Excellent problem-solving skills and attention to detail Strong communication and collaboration skills

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Job Type

Payroll

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Categories

Test Engineer (Engineering )

EDA Engineer (Hardware Engineering)

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Must have Skills

• Verilog - 8 Years
• Universal Verification Methodology - UVM - 8 Years
• Python - 6 Years

  Advanced

• EDA (Electronic Design Automation) - 6 Years

  Advanced

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